- Remember: Attendance on Inkfish.
Important: We need to get set up for next week’s GPIO lab.
Let’s build the rest of the CPU #
- ALU
- Crap, we need an instruction set. Let’s look up RISC-V 32
https://msyksphinz-self.github.io/riscv-isadoc/html/rvi.html
- Add is 00000, 00, rs2:5, rs1:5, 000, rd:5, 01100, 11
- Sub is 00100, 00, rs2:5, rs1:5, 000, rd:5, 01100, 11
- Xor is 00000, 00, rs2:5, rs1:5, 100, rd:5, 01100, 11
Gonna need a register file.
That needs SRAM, which is an array of flip-flops. Each flip-flip is 6 transistors. The overall circuit is is a RAM: you set the address bits, the R/W bit, and it either outputs or inputs a word.
Load / store need RAM.
RAM is slow so we want caches, more details later, but there’s several levels of them.
RAM is slow even with caches, and some operations are slow, so pipelines.
Pipelines stall, so speculative execution.
If we just do multiple things at a time, we’re never wrong, so SMT.
If we just copy the core, we can have multiples, so multi-core.
More cores or fast cores? More cores or wide cores? Cores or cache? Cache or memory channels?
